This invention relates to programmable logic array integrated circuit devices, and more particularly to such devices of the type that have blocks of random access memory ("RAM") that may require programming for use as read-only memory ("ROM").
Cliff et al. U.S. Pat. Nos. 5,550,782 and 5,689,195 show programmable logic array integrated circuit devices with relatively large blocks of random access memory ("RAM") in addition to the usual large number of relatively small programmable logic modules and the usual programmable network of interconnection conductors. (These two prior patents are hereby incorporated by reference herein.) During programming of the other logic on the device, these large RAM blocks may be programmed as read-only memory ("ROM") for use in performing logic functions that may be more efficiently performed in a single relatively large memory block rather than in several relatively small logic modules. Alternatively, these RAM blocks may be used to store data, either in advance of use of the device to perform logic or during use of the device to perform logic.
The typical programmable logic device of the type described above also has a large number of other memory cells that must be programmed before the device can be used to perform logic. For example, these other memory cells determine the logic functions performed by the logic modules on the device, the interconnections that are made throughout the interconnection conductor network, etc. These other memory cells may be arranged in several first-in-first-out ("FIFO") chains for such purposes as programming the individual memory cells and subsequently reading out the contents of those cells in order to verify that they are programming properly. It would be desirable to be able to include the above-mentioned relatively large RAM blocks in such FIFO chains for programming and/or verification. However, this is not easily done because these RAM blocks are not readily addressable by the same logic that is used to address the other memory cells during programming and/or verification.
In view of the foregoing, it is an object of this invention to improve and simplify the circuitry needed to provide and make use of relatively large RAM blocks on programmable logic array integrated circuit devices.
It is a more particular object of this invention to provide improved and simplified circuitry for addressing relatively large RAM blocks on programmable logic array integrated circuit devices during programming and/or verification of those devices.